Semiconductor devices and fabrication methods thereof
US11430657B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 28, 2020 |
| Grant date | Aug 30, 2022 |
| Priority date | — |
| Expiry date | Jul 31, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device includes providing a to-be-etched layer, including alternately arranged first regions and second regions in a first direction. Each first region adjoins adjacent second regions, and each second region includes a trench region. The method includes forming a first mask layer on the to-be-etched layer; implanting doping ions into the first mask layer outside of the trench region; forming a doped separation layer in the first mask layer of the second region to divide the first mask layer into portions arranged in a second direction perpendicular to the first direction; forming a first trench in the first mask layer of the first region; and removing the first mask layer formed in the trench region on both sides of the doped separation layer to form a second trench divided into portions arranged in the second direction by the doped separation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.