Transistor with shield system including multilayer shield structure arrangement
US11430743B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2021 |
| Grant date | Aug 30, 2022 |
| Priority date | — |
| Expiry date | Apr 6, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/65
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor includes a semiconductor substrate having first and second terminals. An interconnect structure, on an upper surface of the substrate, is formed of layers of dielectric material and electrically conductive material. The conductive material includes a first pillar connected with the first terminal, a second pillar connected with the second terminal, and a shield system between the first and second pillars. The shield system includes forked structures formed in at least two conductive layers of the interconnect structure and at least partially surrounding segments of the second pillar. The shield system may additionally include shield traces formed in a first conductive layer positioned between gate fingers and the first pillars and/or the shield system may include shield runners that are located in an electrically conductive layer that is below a topmost electrically conductive layer with the first pillar being connected to a runner in the topmost conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.