Display panel having power bus line with reduced voltage drop
US11430858B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2019 |
| Grant date | Aug 30, 2022 |
| Priority date | — |
| Expiry date | Jun 13, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0262
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display panel includes a substrate including a first non-display area surrounding a transmission area, a display area on an outer portion of the first non-display area, and a second non-display area surrounding the display area, driving thin film transistors and display elements in the display area, a first power supply line in the second non-display area and extending in a first direction, first driving voltage lines and second driving voltage lines extending in a second direction intersecting with the first direction and spaced apart from each other with the transmission area therebetween, and a power bus line connected to the second driving voltage lines in the first non-display area or second non-display area, the power bus line extending in the first direction. A length of the power bus line in the first direction is less than a length of the first power supply line in the first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.