Resistive random access memory device
US11430953B2 · kind B2 · utility
1Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2021 |
| Grant date | Aug 30, 2022 |
| Priority date | — |
| Expiry date | Jan 4, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.