Level shifting circuit and method
US11431339B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 23, 2021 |
| Grant date | Aug 30, 2022 |
| Priority date | — |
| Expiry date | Jul 23, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit includes a bias circuit and a level shifter. The bias circuit includes first and second input terminals configured to receive first and second power supply voltages, and is configured to generate a bias voltage having the greater of a first voltage level of the first power supply voltage or a second voltage level of the second power supply voltage. The level shifter includes a first PMOS transistor configured to receive the first power supply voltage and a second PMOS transistor configured to receive the second power supply voltage, and each of the first and second PMOS transistors includes a bulk terminal configured to receive the bias voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.