Testing a memory which includes conservative reversible logic

US11435940B2 · kind B2 · utility

Assignee

• NXP B.V. · NL

Inventors

• Jan-Peter Schat · Hamburg, DE
• Mohamed Azimane · Eindhoven, NL

Key dates

• Filing date: Feb 2, 2021
• Grant date: Sep 6, 2022
• Expiry date: Mar 14, 2041

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2029/1802
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An integrated circuit device includes an array of read/write memory cells, application logic circuitry, and address decoder circuitry coupled to receive input from the application logic circuitry and to provide output to the array of memory cells. The address decoder circuitry is reversible by having a bijective transfer function from the inputs to the outputs of the address decoder circuitry, and conservative by having the same number of 1's at the input and the output. During a test, the application logic circuitry provides a test value and test ancilla bits to the address decoder circuitry. During normal operation, the application logic circuitry provides an application memory address and constant ancilla bits to the address decoder circuitry.