Matrix transpose hardware acceleration
US11435941B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2020 |
| Grant date | Sep 6, 2022 |
| Priority date | — |
| Expiry date | Aug 15, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one example, an apparatus comprises: a memory array having an array of memory elements arranged in rows and columns, each memory element being configured to store a data element; and a memory access circuit configured to: perform a row write operation to store a first group of data elements at a first row of the array of memory elements; perform a column read operation at a first column of the array of memory elements to obtain a second group of data elements; and perform a column write operation to store a third group of data elements at the first column of the array of memory elements to replace the second group of data elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.