Memory apparatus and control method for command queue based allocation and management of FIFO memories
US11435945B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2019 |
| Grant date | Sep 6, 2022 |
| Priority date | — |
| Expiry date | Oct 10, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a memory apparatus includes a memory device and a controller. The memory device includes a plurality of memory chips. The controller includes a plurality of memories. The controller determines whether or not the memory chip is allocated to any one memory when receiving an access request related to the memory chip from a host apparatus. The controller newly allocates the memory chip to the memory to which none of the memory chips is allocated when it is determined that the memory chips is not allocated, and enqueues a command corresponding to the access request received from the host apparatus to the memory to which the memory chip is newly allocated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.