Arithmetic circuit, and neural processing unit and electronic apparatus including the same
US11435981B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 14, 2020 |
| Grant date | Sep 6, 2022 |
| Priority date | — |
| Expiry date | Apr 14, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arithmetic circuit includes an input buffer latching each of a plurality of input signals, sequentially input, and sequentially outputting a plurality of first addition signals and a plurality of second addition signals based on the plurality of input signals; a first ripple carry adder (RCA) performing a first part of an accumulation operation on the first addition signals to generate a carry; a flip-flop; a second RCA performing a second part of the accumulation operation on the second addition signals and an output of the flop-flop; the first RCA latching the carry in the flip-flop after the accumulation operation is performed; and an output buffer latching an output signal of the first RCA and an output signal of the second RCA, and outputting a sum signal representing a sum of the plurality of input signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.