Smart compute resistive memory
US11436025B2 · kind B2 · utility
1Cited by
2References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2020 |
| Grant date | Sep 6, 2022 |
| Priority date | — |
| Expiry date | Jul 9, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.