Shared buffer for multi-output display systems
US11436171B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2019 |
| Grant date | Sep 6, 2022 |
| Priority date | — |
| Expiry date | Dec 5, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/127
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a display subsystem. The display subsystem includes a shared buffer having allocated portions, each allocated to one of a plurality of display threads, each display thread associated with a display peripheral. The display subsystem also includes a direct memory access (DMA) engine configured to receive a request from a main processor to deallocate an amount of space from a first allocated portion associated with a first display thread. In response to receiving the request, the DMA engine deallocates the amount of space from the first allocated portion and shifts the allocated portions of at least some of other display threads to maintain contiguity of the allocated portions and concatenate free space at an end of the shared buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.