System for placement optimization of chip design for transient noise control and related methods thereof
US11436401B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2019 |
| Grant date | Sep 6, 2022 |
| Priority date | — |
| Expiry date | Sep 16, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Transient voltage noise, including resistive and reactive noise, causes timing errors at runtime. A heuristic framework, Walking Pads, is introduced to minimize transient voltage violations by optimizing power supply pad placement. It is shown that the steady-state optimal design point differs from the transient optimum, and further noise reduction can be achieved with transient optimization. The methodology significantly reduces voltage violations by balancing the average transient voltage noise of the four branches at each pad site. When pad placement is optimized using a representative stressmark, voltage violations are reduced 46-80% across 11 Parsec benchmarks with respect to the results from IR-drop-optimized pad placement. It is shown that the allocation of on-chip decoupling capacitance significantly influences the optimal locations of pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.