Gate driving circuit and display device using the same
US11436983B2 · kind B2 · utility
1Cited by
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17Claims
0Family size
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Key dates
| Filing date | Dec 29, 2020 |
| Grant date | Sep 6, 2022 |
| Priority date | — |
| Expiry date | Dec 29, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A gate driving circuit includes a Q node controller generating a voltage of a Q node by using a first clock, a second clock, a third clock, and a start signal; a QB node controller generating a voltage of a QB node by using the second clock and the third clock; and an output part including a pull-up TFT and a pull-down TFT and generating an output signal including a first pulse interval, of a gate-on voltage, synchronized with a part of the first clock according to the voltages of the Q node and the QB node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.