Multi-phase clock generator, memory device including multi-phase clock generator, and method of generating multi-phase clock of memory device
US11437085B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2020 |
| Grant date | Sep 6, 2022 |
| Priority date | — |
| Expiry date | Dec 31, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-phase clock generator includes first and second variable delay lines, a first phase splitter configured to phase-split a first phase-delayed clock, output from a clock tree, to output a first divided clock and a third divided clock, a second phase splitter configured to phase-split a second phase-delayed clock, output from the clock tree, to output a second divided clock and a fourth divided clock, a first duty cycle detector configured to detect a first duty error between the first divided clock and the third divided clock, and a second duty cycle detector configured to detect a second duty error between the second divided clock and the fourth divided clock. The first variable delay line is controlled according to the first duty error, and the second variable delay line is controlled according to the second duty error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.