Semiconductor memory devices and methods of operating semiconductor memory devices
US11437115B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2021 |
| Grant date | Sep 6, 2022 |
| Priority date | — |
| Expiry date | May 21, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, row fault detector circuitry and control logic circuitry. The memory cell array includes a plurality of memory cell rows. The control logic circuitry controls the ECC engine circuitry to perform a plurality of error detection operations on each of the memory cell rows. The control logic circuitry controls the row fault detector circuitry to store an error parameter associated with each of a plurality of codewords in each of which at least one error is detected by accumulating the error parameter for each of a plurality of defective memory cell rows. The row fault detector circuitry determines whether a row fault occurs in each of the plurality of defective memory cell rows based on a number of changes of the error parameter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.