Field-effect transistors (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals, and related complementary metal oxide semiconductor (CMOS) circuits

US11437379B2 · kind B2 · utility

Assignee

• QUALCOMM Incorporated · US

Inventors

• Stanley Seungchul Song · San Diego, US
• Deepak Sharma · Suwon-si, KR
• Bharani Chava · San Diego, US
• Hyeokjin Lim · San Diego, US
• Peijie Feng · San Diego, US
• Seung H. Kang · San Diego, US
• Jonghae Kim · San Diego, US
• Periannan Chidambaram · San Diego, US
• Kern Rim · Yorktown Heights, US
• Giridhar Nallapati · San Diego, US
• Venugopal Boynapalli · San Marcos, US
• Foua Vang · Lemon Grove, US

Key dates

• Filing date: Sep 18, 2020
• Grant date: Sep 6, 2022
• Expiry date: Nov 3, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6219
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.