Programmable chopping architecture to reduce offset in an analog front end

US11437961B2 · kind B2 · utility

Assignee

• Cypress Semiconductor Corporation · US

Inventors

• Erhan Hancioglu · Bothell, US
• Eashwar Thiagarajan · Bothell, US
• Eric N. Mann · Issaquah, US
• Harold Kutz · Edmonds, US
• Vaibhav Ramamoorthy · Bothell, US
• Rajiv Singh · Natick, US
• Amsby Richardson, Jr. · Lynnwood, US

Key dates

• Filing date: Jun 26, 2020
• Grant date: Sep 6, 2022
• Expiry date: Sep 24, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03F2200/375
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.