Duty cycle correction circuit
US11437985B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2021 |
| Grant date | Sep 6, 2022 |
| Priority date | — |
| Expiry date | Oct 1, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/40
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A duty cycle correction circuit (DCCC) for a multi-modulus frequency divider, the DCCC comprising: a corrector chain comprising a plurality of flip-flops each configured to receive one of the internal signals; and at least one delay selection logic element, each configured to receive an output signal from different ones of the flip-flops and the output of each delay selection logic element is based on the received output signal and the division factor; the DCCC is configured such that: a first state change in its output signal is defined by a transition to a first logic state of one of the internal signals; and a second state change in its output signal is based on a transition to a second logic state of one of the internal signals after a delay period, wherein the duty cycle of the output signal is based on the delay period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.