Systems and methods for optimized re-striping in an erasure encoded storage
US11442644B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2020 |
| Grant date | Sep 13, 2022 |
| Priority date | — |
| Expiry date | Jan 5, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/154
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the present disclosure describe methods and systems for optimized re-striping in an erasure encoded storage. In one exemplary aspect, a method may receive a request to re-stripe a plurality of data blocks arranged as a tile in the erasure encoded storage, wherein the request comprises a desired tile width. The method may identify (1) a number of data blocks in the tile and (2) a width of the tile. The method may determine a maximum number of data blocks that do not need to be rearranged when reconfiguring the tile to the desired tile width. Furthermore, the method may determine a tile reconfiguration with the desired tile width that does not rearrange the maximum number of the data blocks of the tile, and may re-stripe the tile in accordance with the tile reconfiguration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.