Hardware accelerator method, system and device
US11442700B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 27, 2020 |
| Grant date | Sep 13, 2022 |
| Priority date | — |
| Expiry date | Aug 29, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes an addressable memory array, one or more processing cores, and an accelerator framework coupled to the addressable memory. The accelerator framework includes a Multiply ACcumulate (MAC) hardware accelerator cluster. The MAC hardware accelerator cluster has a binary-to-residual converter, which, in operation, converts binary inputs to a residual number system. Converting a binary input to the residual number system includes a reduction modulo 2m and a reduction modulo 2m−1, where m is a positive integer. A plurality of MAC hardware accelerators perform modulo 2m multiply-and-accumulate operations and modulo 2m−1 multiply-and-accumulate operations using the converted binary input. A residual-to-binary converter generates a binary output based on the output of the MAC hardware accelerators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.