Bit-packed array processing using SIMD
US11442729B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2020 |
| Grant date | Sep 13, 2022 |
| Priority date | — |
| Expiry date | Dec 15, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3887
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for processing a bit-packed array using one or more processors, including determining a data element size of the bit-packed array, determining a lane configuration of a single-instruction multiple-data (SIMD) unit for processing the bit-packed array based at least in part on the determined data element size, the lane configuration being determined from among a plurality of candidate lane configurations, each candidate lane configuration having a different number of vector register lanes and a corresponding bit capacity per vector register lane, configuring the SIMD unit according to the determined lane configuration, and loading one or more data elements into each vector register lane of the SIMD unit. SIMD instructions may be executed on the loaded one or more data elements of each vector register lane in parallel, and a result of the SIMD instruction may be stored in memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.