Patent · US Active

Memory sequencer system and a method of memory sequencing using thereof

US11442878B2 · kind B2 · utility

0Cited by

0References

21Claims

0Family size

Assignee

SKYECHIP SDN BHD · MY

Inventors

Chee Hak Teh · Kampung Bukit Kechil, MY
Soon Chieh Lim · Merang, MY

Key dates

Filing date	Feb 6, 2021
Grant date	Sep 13, 2022
Priority date	—
Expiry date	Feb 6, 2041

Classification

Technology area (CPC G)Physics
CPC primaryG06F13/4027
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory sequencer system for external memory protocols including a control center and a microcontroller; a control center network-on-chip having nodes connected point-to-point to synchronize and co-ordinate communication; whereby a command and address sequencer to generate command, control and address commands for specific memory protocols; and at least one data sequencer to generate pseudo-random or deterministic data patterns for each byte lane of a memory interface; wherein said command and address sequencer and said data sequencer are chained to form complex address and data sequences for memory interface training, calibrating and debugging; wherein said control center network-on-chip interconnecting the control center with said command and address sequencer and data sequencer to provide firmware controllability.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.