Sparse matrix multiplier in hardware and a reconfigurable data processor including same
US11443014B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2021 |
| Grant date | Sep 13, 2022 |
| Priority date | — |
| Expiry date | Nov 5, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The technology disclosed relates to matrix multiplication where the multiplier can be a sparse matrix. In particular, a multiplication device includes first circuitry configured to obtain the multiplicand matrix and an index of columns of the multiplier matrix and to generate an intermediate matrix that has one row per entry in the index copied from a respective row of the multiplicand matrix based on a value of a corresponding entry in the index. The device also includes second circuitry configured to receive the intermediate matrix from the first circuitry, obtain non-zero values of the multiplier matrix and a list of a number of non-zero entries per row of the multiplier matrix, and generate a product matrix as a result of multiplies of the non-zero values of the multiplier matrix and the intermediate matrix.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.