Patent · US Active

Techniques for preventing voltage tampering of security control circuits

US11443073B2 · kind B2 · utility

1Cited by

1References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Wei Yee Koay · Kampung Bukit Kechil, MY
Ting Lu · Austin, US
Ching Kooi Hor · Kampung Bukit Kechil, MY
Chin-Ghee Ch'ng · Air Itam, MY

Key dates

Filing date	Dec 17, 2018
Grant date	Sep 13, 2022
Priority date	—
Expiry date	Jan 11, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/17768
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

An integrated circuit includes a comparator circuit that generates a control signal based on a comparison between a threshold voltage and a supply voltage. The integrated circuit also includes a clock signal generation circuit that generates a clock signal and that receives the control signal. The clock signal generation circuit decreases a frequency of the clock signal to a reduced frequency in response to the control signal indicating that the supply voltage has decreased below the threshold voltage. The integrated circuit also includes a secure device manager circuit that has a timing circuit. The clock signal is provided to a clock input of the timing circuit. The timing circuit receives supply current from the supply voltage. The secure device manager circuit performs a security function for the integrated circuit using the timing circuit in response to the clock signal with the reduced frequency.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.