Patent · US Active

Battery life based on inhibited memory refreshes

US11443793B2 · kind B2 · utility

0Cited by

6References

18Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Ramkumar Jayaraman · Kanchinakote, IN
Krishnaprasad H · Bengaluru, IN
Kausik Ghosh · Kanchinakote, IN

Key dates

Filing date	Oct 12, 2020
Grant date	Sep 13, 2022
Priority date	—
Expiry date	Oct 12, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG11C5/148
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Disclosed herein are mechanisms and methods for reducing power consumed by various DRAM technologies (e.g., high-capacity DRAM and/or 3D DRAM) which may impact battery life of the platform. These mechanisms and methods may opportunistically reduce the power consumed by DRAM by inhibiting periodic refresh commands to memory ranks that are not in-use. Since these mechanisms and methods may be based on enhancements to memory controllers, they may accordingly be operating system (OS) agnostic.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.