Array substrate, display panel, method of fabricating display panel, and mother substrate
US11443989B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 8, 2019 |
| Grant date | Sep 13, 2022 |
| Priority date | — |
| Expiry date | Aug 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/73204
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate having a display area, a peripheral area, and a bonding area inside the peripheral area is provided. The array substrate includes a bonding pad in the bonding area, the bonding pad configured to be connected to a peripheral circuit through a bonding connector, a test signal line including a first portion and a second portion. The first portion is in the peripheral area and substantially surrounds the display area. The first portion is electrically connected to the bonding pad. The first portion is completely inside the array substrate and has no exposed terminal. The second portion is in the bonding area. A first terminal of the second portion is electrically connected to the bonding pad. A second terminal of the second portion has an end along an edge of the array substrate in the bonding area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.