Vertical memory device with tri-layer channel
US11444100B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2018 |
| Grant date | Sep 13, 2022 |
| Priority date | — |
| Expiry date | Feb 26, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
Abstract
A vertical memory device and a method of fabricating the same are proposed. The vertical memory device includes a gate stack structure in which gates and interlayer insulating layers for insulating the gates are alternately laminated on a substrate and multiple memory cell areas and inter-memory cell areas are divided in a first direction perpendicular to the substrate; a channel structure extending in the first direction from the substrate to penetrate the gate stack structure; and charge storage elements disposed between the gate stack structure and the channel structure and sequentially formed to be embedded in the gate stack structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.