LDMOS with enhanced safe operating area and method of manufacture
US11444194B2 · kind B2 · utility
0Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Feb 17, 2021 |
| Grant date | Sep 13, 2022 |
| Priority date | — |
| Expiry date | Feb 17, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/378
Abstract
An integrated circuit comprising an n-type drift region, a gate structure directly on a first portion of the n-type drift region, a drain structure formed in a second portion of the n-type drift region, the gate structure and the drain structure being separated by a drift region length, a resist protective oxide (RPO) formed over a portion of the n-type drift region between the gate structure and the drain structure, a field plate contact providing a direct electrical connection to the resist protective oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.