On-chip power supply noise suppression through hyperabrupt junction varactors
US11444210B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2019 |
| Grant date | Sep 13, 2022 |
| Priority date | — |
| Expiry date | Aug 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/6666
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The increasing power density and, therefore, current consumption of high performance integrated circuits (ICs) results in increased challenges in the design of a reliable and efficient on-chip power delivery network. In particular, meeting the stringent on-chip impedance of the IC requires circuit and system techniques to mitigate high frequency noise that results due to resonance between the package inductance and the onchip capacitance. In this paper, a novel circuit technique is proposed to suppress high frequency noise through the use of a hyperabrupt junction tuning varactor diode as a decoupling capacitor for noise critical functional blocks. With the proposed circuit technique, the voltage droops and overshoots on the onchip power distribution network are suppressed by up to 60% as compared to MIM or deep trench decoupling capacitors of the same capacitance. In addition, there is no added latency to react to power supply noise and there is no degradation to circuit performance as compared to existing techniques in commercial products and literature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.