Chip having a receiver including a hysteresis circuit
US11444611B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 14, 2021 |
| Grant date | Sep 13, 2022 |
| Priority date | — |
| Expiry date | Sep 14, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A hysteresis circuit to be produced within a receiver of a chip is shown. The hysteresis circuit is powered by an overdrive voltage (2VDD), and has a protection circuit, an inverter, and a latch. The input of the hysteresis circuit is coupled to the inverter through the protection circuit, to be transformed into an output, and the latch is coupled to the inverter for positive feedback control. The protection circuit has a first sub-circuit (coupling the input to the inverter to control the pull-up path of the inverter) biased by a first bias voltage that is lower than VDD, and a second sub-circuit (coupling the input to the inverter to control the pull-down path of the inverter) biased by a second bias voltage that is greater than VDD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.