Adaptive rate control adjustment for hardware encoder
US11445243B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 8, 2020 |
| Grant date | Sep 13, 2022 |
| Priority date | — |
| Expiry date | May 8, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/4305
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Correcting encode bit rate errors developed by a hardware encoder with an outer software rate adjustment loop. The rate adjustment loop maintains a VBV (video buffering verifier) buffer model. When VBV buffer fullness is over a threshold, the rate adjustment loop drops frames. If below the threshold, periodically a rate adjustment analysis performed. If a number of frames above a threshold have been dropped, the hardware encoder bit rate is decreased. A leaky bucket is checked to determine in bits and out bits. If the number of in bits exceeds the number of out bits times a multiplier, the hardware encoder bit rate is decreased. If the number of in bits times a multiplier is less than the number of out bits, the hardware encoder bit rate is increased. Dropping frames on buffer condition provides shorter term correction and adjustment of the hardware encoder bit rate provides longer term correction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.