Adaptive dynamic clock and voltage scaling
US11449125B1 · kind B1 · utility
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30Claims
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Key dates
| Filing date | Apr 1, 2021 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | Apr 1, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In each of two or more pipelined subsystems, the relative amount of time that the processing cores are idle may be determined. If the idle ratio is below a threshold, the clock frequency and voltage may be adjusted using dynamic clock and voltage scaling (DCVS) based on a power limit. However, if the idle ratio exceeds the threshold, the clock frequency and voltage may be decreased without regard to the power limit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.