Method and apparatus for performing access management of memory device in host performance booster architecture with aid of device side table information
US11449244B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 2021 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | Jun 28, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information are provided. The method may include: sending internal information of the memory device to a host device, to allow the host device to store the internal information of the memory device in a memory within the host device as host side table information at the host device; generating and storing multiple entries of at least one address mapping control table into a random access memory (RAM) as at least one portion of device side table information at the memory device; determining at least two physical addresses associated with at least two logical addresses according to the at least one address mapping control table; and reading data from the NV memory according to the at least two physical addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.