Memory device, data outputting method thereof, and memory system having the same
US11449274B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2021 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | Jun 24, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/101
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes: a memory cell array; a data selector configured to receive data from the memory cell array, and to output the received data as first sub-data and second sub-data; a cyclic redundancy check (CRC) generator configured to generate first CRC values corresponding to the first sub-data, and to generate second CRC values corresponding to the second sub-data; a CRC selector configured to determine an order of the first CRC values and the second CRC values, and to output one of the first CRC values and one of the second CRC values according to the determined order; and a transmitter configured to receive the first CRC values and the second CRC values according to the determined order, and to transmit CRC values of the data by a multilevel signaling method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.