Patent · US Active

Processing and storage circuit

US11449450B2 · kind B2 · utility

0Cited by

2References

17Claims

0Family size

Assignee

RAYMX MICROELECTRONICS, CORP. · CN

Inventors

Shuai Lin · Lianhuan, CN
Yu Zhang · Singapore, SG

Key dates

Filing date	Dec 31, 2020
Grant date	Sep 20, 2022
Priority date	—
Expiry date	Mar 4, 2041

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A processing and storage circuit includes an internal bus, one or more first-level internal memory units, a central processing unit (CPU), one or more hardware acceleration engines, and an arbiter. The first-level internal memory unit is coupled to the internal bus. The CPU includes a second-level internal memory unit, and is configured to access the first-level internal memory unit via the internal bus, and when the CPU accesses data, the first-level internal memory unit is accessed preferentially. The hardware acceleration engine is configured to access the first-level internal memory unit via the internal bus. The arbiter is coupled to the internal bus, configured to decide whether the CPU or the hardware acceleration engine be allowed to access the first-level internal memory unit. The arbiter sets the priority of the CPU accessing the first-level internal memory unit to be over the hardware acceleration engine.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.