Computer system and electronic apparatus having secure boot mechanism and operation status restoring method thereof
US11449614B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 8, 2021 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | Jun 8, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/033
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses an electronic apparatus having secure boot mechanism. The processing circuit executes steps outlined below. Operation-related data is stored in the storage circuit under a normal operation mode. The operation related data is stored in a host terminal. A first hash value is calculated according to the operation related data and is stored in a non-power-off area. A power of the non-power-off area is maintained to be turned on and a power of a power-off area is turned off under a lower power operation mode. The power is restored when the normal operation mode is restored and the operation related data is retrieved from the host terminal to calculate a second hash value. The first and the second hash values are compared such that the operation related data is determined to be valid and the electronic apparatus operates according to the operation related data when the first and the second hash values are matched. The operation related data is determined to be invalid and the electronic apparatus stops to operate when the first and the second hash values are not matched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.