Non-volatile memory circuit and method
US11450395B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2021 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | Apr 22, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a first bank of non-volatile memory (NVM) devices, a first plurality of decoders, a first plurality of high-voltage (HV) drivers corresponding to the first plurality of decoders, and a first plurality of HV power switches. A first HV power switch is coupled to each HV driver of the first plurality of HV drivers, and each decoder is configured to generate an enable signal corresponding to a column of the first bank of NVM devices. Each HV driver is configured to output a HV activation signal to the corresponding column of the first bank of NVM devices responsive to a power signal of the first HV power switch and to the enable signal of the corresponding decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.