Poisoned metal layer with sloped sidewall for making dual damascene interconnect
US11450557B2 · kind B2 · utility
1Cited by
11References
20Claims
0Family size
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Key dates
| Filing date | Feb 26, 2020 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | Mar 17, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53228
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a dual damascene interconnect includes operations of depositing a metal hardmask over a dielectric layer; etching a metal hardmask opening in the metal hardmask to expose a top surface of the dielectric layer; etching at least one interconnect opening in the dielectric layer, to expose a top surface of a base conductive layer; modifying a sidewall of the metal hardmask opening; and depositing a conductive material in the metal hardmask opening and the at least one interconnect opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.