Semiconductor device and method
US11450572B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2020 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | May 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0158
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a device includes: a semiconductor substrate; a first fin extending from the semiconductor substrate; a second fin extending from the semiconductor substrate; an epitaxial source/drain region including: a main layer in the first fin and the second fin, the main layer including a first semiconductor material, the main layer having a upper faceted surface and a lower faceted surface, the upper faceted surface and the lower faceted surface each being raised from respective surfaces of the first fin and the second fin; and a semiconductor contact etch stop layer (CESL) contacting the upper faceted surface and the lower faceted surface of the main layer, the semiconductor CESL including a second semiconductor material, the second semiconductor material being different from the first semiconductor material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.