Vertical semiconductor devices
US11450610B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2020 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | Nov 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertical semiconductor device may include may include a substrate, a stacked structure, an insulating interlayer, a buffer pattern and a first contact plug. The stacked structure may include insulation patterns and conductive patterns stacked on each other on the substrate. The conductive patterns may extend in a first direction parallel to an upper surface of the substrate, and edges of the conductive patterns may have a staircase shape. The conductive patterns may include pad patterns defined by exposed upper surfaces of the conductive patterns. The insulating interlayer may cover the stacked structure. The buffer pattern may be on the insulating interlayer. The first contact plug may pass through the buffer pattern and the insulating interlayer. The first contact plug may contact one of the pad patterns. The buffer pattern may reduce defects from forming the first contact plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.