Semiconductor integrated circuit device
US11450674B2 · kind B2 · utility
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1References
6Claims
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Key dates
| Filing date | Nov 17, 2020 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | Nov 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a ROM cell using a vertical nanowire (VNW) FET, the gate of the VNW FET is connected with a word line (WL), the bottom thereof is connected with a bit line (BL), and the top thereof is selectively connected with a ground potential line. The bottom of the VNW FET of the ROM cell is connected to the bit line (BL) irrespective of the data stored in the ROM cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.