Delay circuit and delay structure
US11451219B2 · kind B2 · utility
3Cited by
16References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2021 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | Aug 18, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00195
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay circuit and a delay structure are provided. The circuit includes: a first delay unit configured to delay a rising edge and/or a falling edge of a pulse signal, where, an input terminal of the first delay unit receives the pulse signal, and an output terminal of the first delay unit outputs a first delay signal, and a second delay unit, configured to delay the first delay signal, where an input terminal of the second delay unit is connected to the output terminal of the first delay unit, and an output terminal of the second delay unit outputs a second delay signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.