Metastabile state detection device and method, and ADC circuit
US11451236B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2020 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | May 9, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A metastable state detection device and method, and an ADC circuit are disclosed. The metastable state detection device includes: a delay unit which is configured to receive a synchronization signal and delay the synchronization signal based on preset step delay values; a first flip-flop unit including a first clock input terminal, a first data input terminal and a first data output terminal, wherein the first clock input terminal is configured to receive a clock signal; the first data input terminal is configured to receive the delayed synchronization signal; a second flip-flop unit including a second clock input terminal, a second data input terminal and a second data output terminal; a processing module connected to the second data output terminal, which is configured to receive a target clock signal and detect a metastable state of the first flip-flop unit according to the target clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.