Multiported parity scoreboard circuit
US11455171B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 29, 2020 |
| Grant date | Sep 27, 2022 |
| Priority date | — |
| Expiry date | May 29, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fast and frugal item-state tracking scoreboard circuit is disclosed. The scoreboard maintains per-item partial states across multiple memory circuits, enabling multiple lookups per clock cycle and multiple state updates per clock cycle. In an embodiment a scoreboard is used to schedule instructions in an out-of-order processor. Each clock cycle the scoreboard indicates the busy state of an instruction's registers and may update the busy state of the destination registers of issuing instructions and completing instructions. Applications include register tracking, function-unit tracking, and cache-line state tracking, in embodiments including processor cores (including superscalar, superpipelined, and multithreaded processors), accelerators, memory systems, and networks. In an embodiment, a register-busy scoreboard circuit is implemented using FPGA LUT RAM memory. In an embodiment, a three-read/two-write per cycle register file scoreboard of 64 registers uses 16 LUTs and indicates whether an instruction is issuable in two LUT delays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.