Energy efficient microprocessor with index selected hardware architecture
US11455272B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2020 |
| Grant date | Sep 27, 2022 |
| Priority date | — |
| Expiry date | Dec 10, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SoC maintains the full flexibility of a general-purpose microprocessor while providing energy efficiency similar to an ASIC by implementing software-controlled virtual hardware architectures that enable the SoC to function as a virtual ASIC. The SoC comprises a plurality of “Stella” Reconfigurable Multiprocessors (SRMs) supported by a Network-on-a-Chip that provides efficient data transfer during program execution. A hierarchy of programmable switches interconnects the programmable elements of each of the SRMs at different levels to form their virtual architectures. Arithmetic, data flow, and interconnect operations are also rendered programmable. An architecture index” points to a storage location where pre-determined hardware architectures are stored and extracted during program execution. The programmed architectures are able to mimic ASIC properties such as variable computation types, bit-resolutions, data flows, and amount and proportions of compute and data flow operations and sizes. Once established, each architecture remains in place as long as needed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.