Patent · US Active

Chip package structure

US11456276B2 · kind B2 · utility

2Cited by

1References

20Claims

0Family size

Assignee

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

Ling Li · Hsinchu, TW
Jung-Hua Chang · Hsinchu, TW
Cheng-Lin Huang · Hsinchu, TW

Key dates

Filing date	Aug 17, 2020
Grant date	Sep 27, 2022
Priority date	—
Expiry date	Aug 20, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/351
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a chip over a first surface of the first substrate. The chip package structure includes a barrier layer over a second surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer and passing through the insulating layer and the barrier layer to connect with the conductive via structure. The chip package structure includes a conductive bump over the conductive pad.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.