Timing margin detecting circuit, timing margin detecting method and clock and data recovery system
US11456749B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2020 |
| Grant date | Sep 27, 2022 |
| Priority date | — |
| Expiry date | Jul 2, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A timing margin detecting circuit is provided. The timing margin detecting circuit comprises a delay element, receiving a first data signal and a first clock signal, configured to generate a second data signal and a second clock signal, wherein the second clock signal has a delay relative to the second data signal; a controller, configured to generate the control signal to control the delay of the second clock signal relative to the second data signal; a sampler, coupled to the delay element, configured to generate a sampled data signal according to the second data signal and the second clock signal; and a bit error rate determination circuit, coupled to the sampler, configured to determine whether the sampled data signal is the same as a predefined test pattern and generate a determination result accordingly; wherein the controller determines a timing margin according to the determination result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.