Augmenting data plane functionality with field programmable integrated circuits
US11456970B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2019 |
| Grant date | Sep 27, 2022 |
| Priority date | — |
| Expiry date | Feb 27, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2212/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Some embodiments provide novel circuits for augmenting the functionality of a data plane circuit of a forwarding element with one or more field programmable circuits and external memory circuits. The external memories in some embodiments serve as deep buffers that receive through one or more FPGAs a set of data messages from the data plane (DP) circuit to store temporarily. In some of these embodiments, one or more of the FPGAs implement schedulers that specify when data messages should be retrieved from the external memories and provided back to the data plane circuit for forwarding through the network. For instance, in some embodiments, a particular FPGA can perform a scheduling operation for a first set of data messages stored in its associated external memory, and can direct another FPGA to perform the scheduling operation for a second set of data messages stored in the particular FPGA's associated external memory. Specifically, in these embodiments, the particular FPGA determines when the first subset of data messages stored in its associated external memory should be forwarded back to the data plane circuit to forward to data messages in the network, while directing another F…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.