Methods and arrangements to accelerate array searches
US11456972B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2018 |
| Grant date | Sep 27, 2022 |
| Priority date | — |
| Expiry date | Oct 17, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/04
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Logic may store at least a portion of an incoming packet at a memory location in a host device in response to a communication from the host device. Logic may compare the incoming packet to a digest in an entry of a primary array. When the incoming packet matches the digest, logic may retrieve a full entry from the secondary array and compare the full entry with the first incoming packet. When the full entry matches the first incoming packet, logic may store at least a portion of the first incoming packet at the memory location. And, in the absence of a match between the first incoming packet and the digest or full entry, logic may compare the first incoming packet to subsequent entries in the primary array to identify a full entry in the secondary array that matches the first incoming packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.