Integrated filter for de-sense reduction
US11457524B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2019 |
| Grant date | Sep 27, 2022 |
| Priority date | — |
| Expiry date | Mar 8, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09609
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A chip includes a plurality of ground conductors that at least partially surround a signal conductor on a same die. The signal conductor carries an interface (e.g., high speed) signal, and the ground conductors filter electromagnetic interference generated by the signal carried by the signal conductor. A chip package includes a plurality of ground pins around a signal pin that carries an interface signal. The ground pins filter electromagnetic interference generated by the signal carried by the signal pin. A printed circuit board includes a plurality of ground conductors around a signal line. The ground conductors are in vias and filter electromagnetic interference generated by an interface signal carried by the signal line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.